verilog, 183 bytes

Result

AC

Duration

1036ms

Code [DL]

`define W $write("
module a;time w,h,t;initial begin t=$fscanf(1<<31,"%d%d",h,w);repeat(w)`W*");`W\n");repeat(h-2)begin `W*");repeat(w-2)`W ");`W*\n");end repeat(w)`W*");end endmodule

stdin

43
50

stdout

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**************************************************

stderr