verilog, 208 bytes

Result

AC

Duration

1020ms

Code [DL]

module a;time w,h;reg t;initial begin t=$fscanf('h8000_0000,"%d%d",h,w);repeat(w)$write("*");$display();repeat(h-2)begin $write("*");repeat(w-2)$write(" ");$display("*");end repeat(w)$write("*");end endmodule

stdin

46
87

stdout

***************************************************************************************
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***************************************************************************************

stderr